Anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level flexibility since any data can be programmed.
Anti-fuse memory can be utilized in all one time programmable applications where it is desired to provide pre-programmed information to a system, in which the information cannot be modified. One example application includes radio frequency identification (RF-ID) tags. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full complementary metal-oxide-semiconductor (CMOS) compatibility of anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes.
FIG. 1 is a circuit diagram illustrating the basic concept of an anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively, of the anti-fuse memory cell shown in FIG. 1. The memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses must be reliable while simple to manufacture with a low cost CMOS process.
FIG. 4a shows a cross-sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process. Variants of this anti-fuse transistor are described in commonly owned U.S. patent application Ser. No. 11/762,552, filed on Jun. 13, 2007, now issued as U.S. Pat. No. 7,755,162 the contents of which are incorporated herein by reference. In the presently shown example, the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output metal oxide semiconductor (MOS) transistor with one floating diffusion terminal. The disclosed anti-fuse transistor, also termed a split-channel capacitor or a half-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device. The cross-section view of FIG. 4a is taken along the channel length of the device, which in the presently described example is a p-channel device.
Anti-fuse transistor 26 includes a variable thickness gate oxide 28 formed on the substrate channel region 30, a polysilicon gate 32, sidewall spacers 34, a field oxide region 36, a diffusion region 38 and a LDD region 40 in the diffusion region 38. A bitline contact 42 is shown to be in electrical contact with diffusion region 38. The variable thickness gate oxide 28 consists of a thick oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur. The thick gate oxide edge meeting diffusion region 38 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 32 and diffusion region 38 is to flow for a programmed anti-fuse transistor. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In this example, the diffusion region 38 is connected to a bitline through a bitline contact 42, or other line for sensing a current from the polysilicon gate 32, and can be doped to accommodate programming voltages or currents. This diffusion region 38 is formed proximate to the thick oxide portion of the variable thickness gate oxide 28. To further protect the edge of anti-fuse transistor 26 from high voltage damage, or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, can be introduced during the fabrication process to further space metal particles from the edge of sidewall spacer 34. This RPO is preferably used during the salicidiation process for preventing only a portion of diffusion region 38 and a portion of polysilicon gate 32 from being salicided. It is well known that salicided transistors are known to have higher leakage and therefore lower breakdown voltage. Thus having a non-salicided diffusion region 38 will reduce leakage. Diffusion region 38 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
A simplified plan view of the anti-fuse transistor 26 is shown in FIG. 4b. Bitline contact 42 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of FIG. 4a. The active area 44 is the region of the device where the channel region 30 and diffusion region 38 are formed, which is defined by an OD mask during the fabrication process. The dashed outline 46 defines the areas in which the thick gate oxide is to be formed via an OD2 mask during the fabrication process. More specifically, the area enclosed by the dashed outline 46 designates the regions where thick oxide is to be formed. OD simply refers to an oxide definition mask that is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed, and OD2 refers to a second oxide definition mask different than the first. Details of the CMOS process steps for fabricating anti-fuse transistor 26 are discussed in previously mentioned U.S. Pat. No. 7,755,162. In one embodiment, the thin gate oxide area bounded by edges of the active area 44 and the rightmost edge of the OD2 mask is minimized. In the presently shown embodiment, this area can be minimized by shifting the rightmost OD2 mask edge towards the parallel edge of active area 44. Previously mentioned U.S. Pat. No. 7,755,162 describes alternate single transistor anti-fuse memory cells which can be used in a non-volatile memory array.
FIG. 5 is a simplified schematic of a non-volatile memory array 50 which uses the previously described anti-fuse device, wherein each memory cell 51 comprises an instance of the anti-fuse device. Programming of a selected memory cell 51 is achieved by biasing a bitline 52 connected to the selected memory cell 51 to a program enabling voltage, such as VSS by example. To prevent programming of a selected memory cell 51 and/or non-selected memory cells 51, the bitline 52 is biased to a program inhibiting voltage, such as a positive voltage by example. For this purpose, the bitlines 52 are connected to N channel precharge devices 59 receiving PCH 53 and the precharge voltage VPCH 54. It is noted that VPCH can be set to different voltage levels for program and read cycles. VPCH can be set to a program inhibit voltage level, which in the present embodiments can be a high voltage level sufficient for inhibiting programming of non-selected memory cells. For read cycles, VPCH can be set to a voltage level lower than the program inhibit voltage level.
In FIG. 5, PCH 53 is activated for a short period of time in a precharge operation of a programming cycle to couple all the bitlines 52 to precharge voltage VPCH 54. It should be understood that a programming cycle includes a precharge operation followed by a programming operation to program data to cells addressed by a row and column address. Subsequent programming cycles can be executed for either re-programming the same cells or for programming different cells. Then all the bitlines 52 float when precharge devices 59 are turned off. Then one of the column select devices 55 is turned on by activating one of the column select signals Y[0] to Y[7] to couple the selected bitline 52 to BLSA 56, which is biased by sense amplifier (SA) 58 to VSS. For read operations, sense amplifier 58 compares the voltage of BLSA from the selected bitline to a reference voltage carried on line BLSAb. In program operations, sense amplifier 58 is configured to bias the selected bitline to VSS or VDD depending on the write data. In alternate configurations, a separate write circuit can be used to provide the write data to the selected bitline. An isolation device 61 is also provided selectively to connect BLSA 56 commonly to the column select devices 55. In the programming operation, a selected word line 57 is driven to a programming voltage level. Accordingly, the memory cell 51 connected to the selected word line 57 at the programming voltage level and the bitline 52 at VSS will be programmed. Conversely, any memory cell 51 connected to the selected word line 57 and a bitline 52 at VPCH 54 should be inhibited from being programmed.
The problem with this scheme is that the non-selected bitlines having been pre-charged to the VPCH level will experience leakage through various sources. This means that the VPCH level will decay, or slowly discharge, towards VSS. Hence the non-selected bitlines may not be fully inhibited from being programmed when the word line is driven to the programming voltage level. Therefore non-selected memory cell may be inadvertently programmed. This is referred to as write disturb.
FIG. 6 is a timing diagram showing schematically the bitline voltages for non-selected bitlines and a selected bitline not to be programmed in a programming cycle for the circuit of FIG. 5. Signal traces for the PCH signal, selected and non-selected column select signals Y, the ISOL signal, a selected bitline to be programmed, a selected bitline inhibited from being programmed, and a non-selected bitline are shown. It is noted that the timing diagram signal traces are not drawn to scale, and the bitline voltage signal traces are drawn with an enlarged scale relative to the other shown signals in order to better illustrate the voltage changes occurring therein.
As shown in the diagram, the PCH signal is pulsed to the active logic high level for precharging all the bitlines as part of the precharge operation of the programming cycle. In the presently shown example of FIG. 6, the bitlines can be precharged to a read precharge voltage of about Vx-Vt in preparation for a read operation, or to about VCC-Vt in preparation for a programming operation. Both levels are illustrated in FIG. 6. During the high PCH pulse, the column select signals Y are at the inactive low logic level to keep the column select devices 55 turned off. Signal ISOL is also at the inactive low logic level during the PCH pulse to keep isolation device 61 turned off. It is assumed during this time that the sense amplifier 58 has been loaded with write data having either a high or low logic level.
At the end of the PCH pulse the precharge operation ends and the program operation commences with a selected Y column select signal driven to the high logic level as shown in the solid black line, while non-selected Y column select signals remain at the low logic level as shown in the dashed line. At about the same time, ISOL is driven to the high logic level to connect BLSA 56 to the selected bitline via the selected Y column select signal. If programming is required for the cell connected to the selected bitline, BLSA is at the low logic level to drive the selected bitline to VSS as shown by the dashed line. Otherwise if no programming is required, then the selected bitline voltage decays from the VCC-Vt precharge voltage to about VDD-Vt as shown by the solid line. In this particular example embodiment, the VDD-Vt voltage is provided by the sense amplifier. However, the initially precharged non-selected bitlines will decay towards VSS, and are therefore susceptible to erroneous and undesirable programming, or write disturb when the selected wordline is driven. In the present example, the non-selected bitlines will have decayed to VSS at about 1 μs, which is at least the time required for completion of a programming cycle in some examples.
The non-selected bitlines decay to these levels because of bitline leakage. In the presently shown example timing diagram, VCC is the IO supply voltage and can be 1.8V, 2.5V, or 3.3V by example, VDD is the core logic voltage and can be 0.9V, 1.0V, or 1.1V by example, and VX is the read voltage and can be in the range of 1.3V to 2.2V depending on the process by example. VX is derived from VCC and can be lower than VCC, but in alternate embodiments can be greater than VCC.
It is, therefore, desirable to provide a circuit and method for minimizing write disturb in OTP memories.